1. Field of the Invention
The present invention relates to a hetero-junction bipolar transistor and a method of manufacturing the same, and more particularly, to a hetero-junction bipolar transistor that can increase data processing speed by reducing base resistance and parasitic capacitance and a method of manufacturing the same.
2. Description of the Related Art
A hetero-junction bipolar transistor (HBT) is a core device in microwave or millimeter wave band technologies that requires high speed characteristics. The HBT consists of a three-phase electrode composed of an emitter, a base, and a collector. In particular, the emitter of the HBT is formed of a semiconductor material having a higher energy bandwidth than the base so that a high current gain and a high cut-off frequency can be obtained.
Here, the cut-off frequency is related to the resistance of the base. That is, to increase the cut-off frequency, a thickness and/or concentration of a base material can be changed or a base electrode can be located as close as possible to the emitter electrode. Currently, the HBTs are formed using a method in which the base electrode and the emitter electrode are closely disposed to each other in a self aligning manner in a state where the thickness and the concentration of the base material are optimized. This method is shown in FIGS. 1 and 2.
Referring to FIG. 1, an n+ InGaAs sub-collector layer 12, an n− InGaAs collector layer 13, a p+ InGaAs base layer 14, an n InP emitter layer 15, an n+ InP emitter grade layer 16, and an n+ InGaAs emitter cap layer 17 are sequentially formed on a semi-insulated InP substrate 11.
Referring to FIG. 2, after a patterned emitter electrode 20 is formed on the n+ InGaAs emitter cap layer 17, the n+ InGaAs emitter cap layer 17, the n+ InP emitter grade layer 16, and the n InP emitter layer 15 are etched using the emitter electrode 20 as a mask. Then, the n+ InGaAs emitter cap layer 17, the n+ InP emitter grade layer 16, and the n InP emitter layer 15 are over-etched using a wet etching method. As a result, the n+ InGaAs emitter cap layer 17, the n+ InP emitter grade layer 16, the n InP emitter layer 15, and the emitter electrode 20 have an under-cut structure.
Afterward, a base electrode 21 is selectively formed on the exposed p+ InGaAs base layer 14. The base electrode 21 is formed in a self-aligning manner by the under-cut structure of the emitter electrode 20 and the emitter material layers 17, 16, and 15. Next, a photoresist pattern (not shown) covering predetermined portions of the emitter electrode 20 and the base electrode 21 is formed. An HBT region is defined and the n+ InGaAs sub-collector layer 12 is exposed by etching the base electrode 21, the p+ InGaAs base layer 14, and the n− InGaAs collector layer 13 using the photoresist pattern. At this time the n− InGaAs collector layer 13 has a thickness usually greater than the p+ InGaAs base layer 14. To etch the n− InGaAs collector layer 13 which is relatively thick , a directional etching and/or isotropic wet etching can be performed. Then a collector electrode 12 (not shown) is formed in a predetermined portion of the n+ InGaAs sub-collector layer 12.
However, when the emitter material layer is over-etched to form the base electrode 21 in a self-aligning manner as described above, a portion of the p+ InGaAs base layer 14 may be lost. Also, when the p+ InGaAs base layer 14 and the n− InGaAs collector layer 13 are etched to define the HBT region, the p+ InGaAs base layer 14 disposed on the n− InGaAs collector layer 13 can be over-etched due to the directional etching and/or the isotropic etching of the n− InGaAs collector layer 13. When the p+ InGaAs base layer 14 is over-etched, the base electrode 21 formed on the p+ InGaAs base layer 14 may be lifted, and the resistance of the p+ InGaAs base layer 14 can be increased due to its reduced thickness.
Also, since a lower surface of the conventional base electrode 21 is formed to contact an upper surface of the p+ InGaAs base layer 14, an area for forming the base electrode 21 must be ensured on the p+ InGaAs base layer 14. At this time, since the n− InGaAs collector layer 13 formed under the p+ InGaAs base layer 14 is simultaneously defined with the p+ InGaAs base layer 14, a predetermined junction area between the n− InGaAs collector layer 13 and the p+ InGaAs base layer 14 must be ensured. Therefore, a problem of increased junction capacitance between the base and the collector occurs. Also, in the HBT of FIG. 2, side surfaces of the junction area of the n− InGaAs collector layer 13 and the p+ InGaAs base layer 14 are exposed externally, thereby increasing parasitic junction capacitance.
When the resistance of the p+ InGaAs base layer 14 is increased and the junction capacitance between the base and the collector is increased, RC delay time may be increased, thereby reducing operating speed of the HBT.